104 search results - page 2 / 21 » Addressable test ports an approach to testing embedded cores |
ICCAD
2007
IEEE
13 years 9 months ago
2007
IEEE
Abstract-- In this paper, we propose a novel test data compression technique named CacheCompress, which combines selective encoding and dynamic dictionary based encoding. Depending...
ITC
2002
IEEE
13 years 10 months ago
2002
IEEE
DAC
2001
ACM
14 years 6 months ago
2001
ACM
Crosstalk effects degrade the integrity of signals traveling on long interconnects and must be addressed during manufacturing testing. External testing for crosstalk is expensive ...
ITC
1997
IEEE
13 years 10 months ago
1997
IEEE
Testing embedded cores is a challenge because access to core I/Os is limited. The user-defined logic (ZJDL) surrounding the core may restrict the set of test vectors that can be a...
ATS
2000
IEEE
13 years 10 months ago
2000
IEEE
Testing of embedded cores is very difficult in SOC (system-on-a-chip), since the core user may not know the gate level implementation of the core, and the controllability and obse...