19 search results - page 1 / 4 » Addressing the Timing Closure Problem by Integrating Logic O... |
ICCAD
2001
IEEE
14 years 1 months ago
2001
IEEE
Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation...
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
: In this paper, an algorithm for simultaneous logic restructuring and placement is presented. This algorithm first constructs a set of super-cells along the critical paths and the...
ISPD
2010
ACM
13 years 11 months ago
2010
ACM
Timing-driven placement is a critical step in nanometerscale physical synthesis. To improve design timing on a global scale, net-weight based global timing-driven placement is a c...
DAC
2005
ACM
14 years 5 months ago
2005
ACM
Placement migration is the movement of cells within an existing placement to address a variety of post-placement design closure issues, such as timing, routing congestion, signal ...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
Placement migration is a critical step to address a variety of postplacement design closure issues, such as timing, routing congestion, signal integrity, and heat distribution. To...