19 search results - page 2 / 4 » Addressing the Timing Closure Problem by Integrating Logic O... |
DAC
2007
ACM
14 years 6 months ago
2007
ACM
Abstract-- In nanometer-scale VLSI technologies, several interconnect issues like routing congestion and interconnect delay have become the main concerns in placement. However, all...
VLSID
2002
IEEE
13 years 10 months ago
2002
IEEE
We propose a timing-oriented logic optimization technique called Generalized De Morgan (GDM) transform, that integrates gate resizing, net buffering and De Morgan transformation. ...
ICCAD
2008
IEEE
14 years 2 months ago
2008
IEEE
—When manufacturing nano-devices, defects are a certainty and reliability becomes a critical issue. Until now, the most pervasive methods used to address reliability, involve inj...
FPGA
2004
ACM
13 years 9 months ago
2004
ACM
This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and p...
HEURISTICS
2002
13 years 5 months ago
2002
In this paper, we present the parallelization of tabu search on a network of workstations using PVM. Two parallelization strategies are integrated: functional decomposition strate...