Sciweavers

23 search results - page 3 / 5
» An ASIC perspective on FPGA optimizations
Sort
View
FPGA
2007
ACM
106views FPGA» more  FPGA 2007»
14 years 5 days ago
A synthesizable datapath-oriented embedded FPGA fabric
We present an architecture for a synthesizable datapathoriented Field Programmable Gate Array (FPGA) core which can be used to provide post-fabrication flexibility to a Systemon-...
Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai ...
ASAP
2008
IEEE
146views Hardware» more  ASAP 2008»
14 years 15 days ago
A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator
Many complex systems require the use of floating point arithmetic that is exceedingly time consuming to perform on personal computers. However, floating point operators are also h...
Jason Lee, Lesley Shannon, Matthew J. Yedlin, Gary...
ICCS
2009
Springer
14 years 17 days ago
A Massively Parallel Architecture for Bioinformatics
Abstract. Today’s general purpose computers lack in meeting the requirements on computing performance for standard applications in bioinformatics like DNA sequence alignment, err...
Gerd Pfeiffer, Stefan Baumgart, Jan Schröder,...
FPGA
2009
ACM
188views FPGA» more  FPGA 2009»
14 years 24 days ago
Clock power reduction for virtex-5 FPGAs
Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presen...
Qiang Wang, Subodh Gupta, Jason Helge Anderson
DAC
2004
ACM
14 years 7 months ago
Automated fixed-point data-type optimization tool for signal processing and communication systems
A tool that automates the floating-point to fixed-point conversion (FFC) process for digital signal processing systems is described. The tool automatically optimizes fixed-point d...
Changchun Shi, Robert W. Brodersen