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» An Efficient VLIW DSP Architecture for Baseband Processing
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ICCD
2003
IEEE
147views Hardware» more  ICCD 2003»
14 years 1 months ago
An Efficient VLIW DSP Architecture for Baseband Processing
The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for highperformance real-time DSP applications. But the two major w...
Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-...
DSD
2009
IEEE
387views Hardware» more  DSD 2009»
13 years 11 months ago
Architecture and DSP Implementation of a DVB-S2 Baseband Demodulator
—This paper presents the design and implementation of a baseband demodulator for DVB-S2 satellite receivers. In order to meet the requirements of different complex and multidomai...
Panayiotis Savvopoulos, Nikolaos Papandreou, Theod...
ISSS
2002
IEEE
174views Hardware» more  ISSS 2002»
13 years 9 months ago
A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor
Nowadays, new DSP applications are offering combined and flexible multimedia and telecom services. VLIW processor architectures, which include dedicated but inflexible functional ...
Carles Rodoreda Sala, Natalino G. Busá
IWSOC
2005
IEEE
151views Hardware» more  IWSOC 2005»
13 years 10 months ago
A Low Area and Low Power Programmable Baseband Processor Architecture
A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a con...
Eric Tell, Anders Nilsson, Dake Liu
VLSISP
2008
159views more  VLSISP 2008»
13 years 4 months ago
Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores
The compiler is generally regarded as the most important software component that supports a processor design to achieve success. This paper describes our application of the open re...
Yung-Chia Lin, Chia-Han Lu, Chung-Ju Wu, Chung-Lin...