Sciweavers

11 search results - page 1 / 3
» An Integrated Hot-Carrier Degradation Simulator for VLSI Rel...
Sort
View
DATE
2010
IEEE
161views Hardware» more  DATE 2010»
13 years 10 months ago
Aging-resilient design of pipelined architectures using novel detection and correction circuits
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...
Hamed F. Dadgour, Kaustav Banerjee
GLVLSI
2006
IEEE
112views VLSI» more  GLVLSI 2006»
13 years 11 months ago
A simulation methodology for reliability analysis in multi-core SoCs
Reliability has become a significant challenge for system design in new process technologies. Higher integration levels dramatically increase power densities, which leads to high...
Ayse Kivilcim Coskun, Tajana Simunic Rosing, Yusuf...
ICCD
2001
IEEE
213views Hardware» more  ICCD 2001»
14 years 2 months ago
Analysis and Reduction of Capacitive Coupling Noise in High-Speed VLSI Circuits
Abstract-- Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock frequency to 2GHz has caused crosstalk noise to become a serious problem, that degr...
Payam Heydari, Massoud Pedram
ISQED
2008
IEEE
103views Hardware» more  ISQED 2008»
13 years 11 months ago
Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation
Negative bias temperature instability (NBTI) is one of the primary limiters of reliability lifetime in nano-scale integrated circuits. NBTI manifests itself in a gradual increase ...
Bin Zhang, Michael Orshansky