18 search results - page 2 / 4 » An analytical approach for soft error rate estimation in dig... |
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
Soft errors have emerged as an important reliability challenge for nanoscale VLSI designs. In this paper, we present a fast and efficient soft error rate (SER) computation algorit...
FPGA
2005
ACM
13 years 11 months ago
2005
ACM
FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs. Soft error rate (SER) estimation is a crucial step in the design of soft error tole...
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
In this paper, we present an accurate but very fast soft error rate (SER) estimation technique for digital circuits based on error propagation probability (EPP) computation. Exper...
DATE
2008
IEEE
13 years 12 months ago
2008
IEEE
In the last decade, the focus of fault-tolerance methods has tended towards circuit level modifications, such as transistor resizing, and away from expensive system level redunda...
DATE
2009
IEEE
14 years 4 days ago
2009
IEEE
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...