Sciweavers

19 search results - page 1 / 4
» An efficient technique for device and interconnect optimizat...
Sort
View
ISPD
1998
ACM
88views Hardware» more  ISPD 1998»
13 years 9 months ago
An efficient technique for device and interconnect optimization in deep submicron designs
In this paper, we formulate a new class of optimization problem, named the general CH-posynomial program, and reveal the general dominance property. We propose an efcient algorith...
Jason Cong, Lei He
ICCAD
1997
IEEE
86views Hardware» more  ICCAD 1997»
13 years 9 months ago
Interconnect design for deep submicron ICs
Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends...
Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok K...
DAC
2001
ACM
14 years 5 months ago
Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
Kaustav Banerjee, Amit Mehrotra
DAC
1998
ACM
13 years 9 months ago
Global Routing with Crosstalk Constraints
—Due to the scaling down of device geometry and increasing of frequency in deep submicron designs, crosstalk between interconnection wires has become an important issue in very l...
Hai Zhou, D. F. Wong
ISQED
2006
IEEE
118views Hardware» more  ISQED 2006»
13 years 11 months ago
Design of a Single Event Upset (SEU) Mitigation Technique for Programmable Devices
This paper presents a unique SEU (single Event Upset) mitigation technique based upon Temporal Data Sampling for synchronous circuits and configuration bit storage for programmabl...
Sajid Baloch, Tughrul Arslan, Adrian Stoica