111 search results - page 2 / 23 » Analysis of power consumption in VLSI global interconnects |
TC
2008
13 years 5 months ago
2008
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
GLVLSI
2006
IEEE
13 years 11 months ago
2006
IEEE
A sensitivity analysis of resonant H-tree clock distribution networks is presented in this paper for a TSMC 0.18 μm CMOS technology. The analysis focuses on the effect of the dri...
AINA
2007
IEEE
13 years 11 months ago
2007
IEEE
Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessor...
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
Designing NoC-based systems has become increasingly complex with support for multiple functionalities. Decisions regarding interconnections between the heterogeneous system compon...
DAC
2002
ACM
14 years 6 months ago
2002
ACM
In this paper, we introduce a framework to estimate the power consumption on switch fabrics in network routers. We propose different modeling methodologies for node switches, inte...