10 search results - page 1 / 2 » Analyzing Soft Errors in Leakage Optimized SRAM Design |
VLSID
2003
IEEE
14 years 5 months ago
2003
IEEE
Reducing leakage power and improving the reliability of data stored in the memory cells are both becoming challenging as technology scales down. While the smaller threshold voltag...
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
Soft errors that change configuration bits of an SRAM based FPGA modify the functionality of the design. The proliferation of FPGA devices in various critical applications makes it...
ISQED
2008
IEEE
13 years 11 months ago
2008
IEEE
We present an error-tolerant SRAM design optimized for ultra-low standby power. Using SRAM cell optimization techniques, the maximum data retention voltage (DRV) of a 90nm 26kb SR...
VLSID
2009
IEEE
14 years 5 months ago
2009
IEEE
We analyze the neutron induced soft error rate (SER). An induced error pulse is modeled by two parameters, probability of occurrence and probability density function of the pulse ...
PATMOS
2007
Springer
13 years 11 months ago
2007
Springer
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...