Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation

We present an error-tolerant SRAM design optimized for ultra-low standby power. Using SRAM cell optimization techniques, the maximum data retention voltage (DRV) of a 90nm 26kb SRAM module is reduced from 550mV to 220mV. A novel errortolerant architecture further reduces the minimum static-error-free VDD to 155mV. With a 100mV noise margin, a 255mV standby VDD effectively reduces the SRAM leakage power by 98% compared to the typical standby at 1V VDD.

• Type: Conference
• Year: 2008
• Where: ISQED
• Authors: Huifang Qin, Animesh Kumar, Kannan Ramchandran, Jan M. Rabaey, Prakash Ishwar
• Keywords: Error-tolerant Sram Design, Hardware, ISQED 2008, SRAM Cell Optimization, Ultra-low Standby Power