Sciweavers

10 search results - page 2 / 2
» Analyzing Soft Errors in Leakage Optimized SRAM Design
Sort
View
TCAD
2008
172views more  TCAD 2008»
13 years 5 months ago
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodr...
DAC
2008
ACM
14 years 6 months ago
Study of the effects of MBUs on the reliability of a 150 nm SRAM device
1 Soft errors induced by radiation are an increasing problem in the microelectronic field. Although traditional models estimate the reliability of memories suffering Single Event U...
Juan Antonio Maestro, Pedro Reviriego
HPCA
2009
IEEE
14 years 11 days ago
Soft error vulnerability aware process variation mitigation
As transistor process technology approaches the nanometer scale, process variation significantly affects the design and optimization of high performance microprocessors. Prior stu...
Xin Fu, Tao Li, José A. B. Fortes
DATE
2010
IEEE
158views Hardware» more  DATE 2010»
13 years 10 months ago
Energy- and endurance-aware design of phase change memory caches
—Phase change memory (PCM) is one of the most promising technology among emerging non-volatile random access memory technologies. Implementing a cache memory using PCM provides m...
Yongsoo Joo, Dimin Niu, Xiangyu Dong, Guangyu Sun,...
CHES
2003
Springer
100views Cryptology» more  CHES 2003»
13 years 10 months ago
Multi-channel Attacks
We introduce multi-channel attacks, i.e., side-channel attacks which utilize multiple side-channels such as power and EM simultaneously. We propose an adversarial model which combi...
Dakshi Agrawal, Josyula R. Rao, Pankaj Rohatgi