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HIPEAC
2007
Springer
13 years 11 months ago
Applying Decay to Reduce Dynamic Power in Set-Associative Caches
Abstract. In this paper, we propose a novel approach to reduce dynamic power in set-associative caches that leverages on a leakage-saving proposal, namely Cache Decay. We thus open...
Georgios Keramidas, Polychronis Xekalakis, Stefano...
PACS
2000
Springer
121views Hardware» more  PACS 2000»
13 years 9 months ago
Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power
Reducing the supply voltage to reduce dynamic power consumption in CMOS devices, inadvertently will lead to an exponential increase in leakage power dissipation. In this work we ex...
Stefanos Kaxiras, Zhigang Hu, Girija J. Narlikar, ...
EUC
2004
Springer
13 years 10 months ago
Non-uniform Set-Associative Caches for Power-Aware Embedded Processors
Abstract. Power consumption is becoming one of the most important constraints for microprocessor design in nanometer-scale technologies. Especially, as the transistor supply voltag...
Seiichiro Fujii, Toshinori Sato
CF
2005
ACM
13 years 7 months ago
Skewed caches from a low-power perspective
The common approach to reduce cache conflicts is to increase the associativity. From a dynamic power perspective this associativity comes at a high cost. In this paper we present...
Mathias Spjuth, Martin Karlsson, Erik Hagersten
CF
2007
ACM
13 years 9 months ago
Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors
Energy-efficient microprocessor designs are one of the major concerns in both high performance and embedded processor domains. Furthermore, as process technology advances toward d...
Juan M. Cebrian, Juan L. Aragón, José...