130 search results - page 4 / 26 » Architecture and Evaluation of an Asynchronous Array of Simp... |
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper we present a systematic comparison between two different implementations of a distributed Network on Chip: fully asynchronous and multi-synchronous. The NoC architec...
ARVLSI
1999
IEEE
13 years 9 months ago
1999
IEEE
Application-specific processor design is a promising approach for meeting the performance and cost goals of a system. Application-specific processors are especially promising for ...
ASPLOS
2004
ACM
13 years 10 months ago
2004
ACM
We present a novel processor architecture designed specifically for use in low-power wireless sensor-network nodes. Our sensor network asynchronous processor (SNAP/LE) is based on...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
ICCD
2000
IEEE
2000
IEEE
Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Superscalar Architectures
13 years 9 months ago
This paper aims to provide a quantitative understanding of the performance of DSP and multimedia applications on very long instruction word (VLIW), single instruction multiple dat...