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ISCAS
2005
IEEE
95views Hardware» more  ISCAS 2005»
13 years 10 months ago
Area, power, and pin efficient bus transceiver using multi-bit-differential signaling
—This paper describes a new low-power, area and pin efficient alternative to differential encoding for high performance chip-to-chip and backplane signaling. The technique, calle...
Donald M. Chiarulli, Jason D. Bakos, Joel R. Marti...
VTS
2005
IEEE
151views Hardware» more  VTS 2005»
13 years 10 months ago
A CMOS RF RMS Detector for Built-in Testing of Wireless Transceivers
: This project involves the design of a CMOS RF RMS Detector that converts the RMS voltage amplitude of an RF signal to a DC voltage. Its high input impedance and small area make i...
Alberto Valdes-Garcia, Radhika Venkatasubramanian,...
GLVLSI
2006
IEEE
152views VLSI» more  GLVLSI 2006»
13 years 10 months ago
2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as c...
Rashed Zafar Bhatti, Monty Denneau, Jeff Draper