22 search results - page 1 / 5 » Area Optimizations for Dual-Rail Circuits Using Relative-Tim... |
ASYNC
2007
IEEE
13 years 11 months ago
2007
IEEE
Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. Howev...
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ens...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
Smart cards are vulnerable to both invasive and non-invasive attacks. Specifically, non-invasive attacks using power and timing measurements to extract the cryptographic key has d...
DAC
2005
ACM
13 years 6 months ago
2005
ACM
In this paper, we propose a new sensitivity based, statistical gate sizing method. Since circuit optimization effects the entire shape of the circuit delay distribution, it is dif...
ISQED
2008
IEEE
13 years 11 months ago
2008
IEEE
The effects of random variations during the manufacturing process on devices can be simulated as a variation of transistor parameters. Device degradation, due to temperature or vo...