12 search results - page 2 / 3 » Area fill synthesis for uniform layout density |
VLSID
1999
IEEE
13 years 9 months ago
1999
IEEE
To reduce manufacturing variation due to chemicalmechanical polishing and to improve yield, layout must be made uniform with respect to density criteria. This is achieved by layou...
TCAD
2008
13 years 4 months ago
2008
We survey recent research and practice in the area of chemical
ISPD
2010
ACM
13 years 11 months ago
2010
ACM
In the nanometer IC design, dummy fill is often performed to improve layout pattern uniformity and the post-CMP quality. However, filling dummies might greatly increase intercon...
ASPDAC
1999
ACM
13 years 9 months ago
1999
ACM
Certain manufacturing steps in very deep submicron VLSI involve chemical-mechanical polishing CMP which has varying e ects on device and interconnect features, depending on loca...
DAC
2009
ACM
14 years 6 months ago
2009
ACM
Abstract--To reduce chip-scale topography variation in Chemical Mechanical Polishing (CMP) process, dummy fill is widely used to improve the layout density uniformity. Previous res...