27 search results - page 2 / 6 » Area-efficient error protection for caches |
ISCA
2009
IEEE
13 years 12 months ago
2009
IEEE
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...
ICCD
2006
IEEE
14 years 2 months ago
2006
IEEE
Abstract-- We deconstruct and compare the two dominant existing approaches for L1 data cache (L1D) error protection, with respect to performance, L2 cache bandwidth, power, and are...
CASES
2006
ACM
13 years 11 months ago
2006
ACM
With advances in process technology, soft errors (SE) are becoming an increasingly critical design concern. Due to their large area and high density, caches are worst hit by soft ...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
ISCA
2011
IEEE
12 years 9 months ago
2011
IEEE
Due to shrinking feature sizes processors are becoming more vulnerable to soft errors. Write-back caches are particularly vulnerable since they hold dirty data that do not exist i...