Sciweavers

30 search results - page 3 / 6
» Automatic generation of breakpoint hardware for silicon debu...
Sort
View
TODAES
2008
115views more  TODAES 2008»
13 years 4 months ago
Automata-based assertion-checker synthesis of PSL properties
Abstract-- Automata-based methods for generating PSL hardware assertion checkers were primarily considered for use with temporal sequences, as opposed to full-scale properties. We ...
Marc Boule, Zeljko Zilic
ASAP
2008
IEEE
105views Hardware» more  ASAP 2008»
13 years 6 months ago
Fast custom instruction identification by convex subgraph enumeration
Automatic generation of custom instruction processors from high-level application descriptions enables fast design space exploration, while offering very favorable performance and...
Kubilay Atasu, Oskar Mencer, Wayne Luk, Can C. &Ou...
DATE
2003
IEEE
112views Hardware» more  DATE 2003»
13 years 10 months ago
Automatic Generation of Simulation Monitors from Quantitative Constraint Formula
System design methodology is poised to become the next big enabler for highly sophisticated electronic products. Design verification continues to be a major challenge and simulat...
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Wat...
FPL
2005
Springer
89views Hardware» more  FPL 2005»
13 years 10 months ago
Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC
Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run-time reconfigurabil...
Mark Holland, Scott Hauck
FPL
2004
Springer
101views Hardware» more  FPL 2004»
13 years 10 months ago
Automatic Creation of Reconfigurable PALs/PLAs for SoC
Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run -time reconfigurabil...
Mark Holland, Scott Hauck