A fault-oriented sequential circuit test generator is described in which various types of distinguishing sequences are derived, both statically and dynamically, to aid the test ge...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
Our goal is to transform a low-level circuit design into a more representation. A pre-existing tool, Tranalyze [4], takes a switch-level circuit and generates a functionally equiv...
This paper presents new test generation techniques for improving the average-case performance of the iterative logic array based deterministic sequential circuit test generation a...
A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning ...
A new statistical technique for average power estimation in sequential circuits is presented. Due to the feedback mechanism, conventional statistical procedures cannot be applied ...