115 search results - page 2 / 23 » Automatic generation of transaction level models for rapid d... |
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper gives an overview of a transaction level modeling (TLM) design flow for straightforward embedded system design with SystemC. The goal is to systematically develop both...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
LCTRTS
2010
Springer
13 years 11 months ago
2010
Springer
With increasingly more complex Multi-Processor Systems on Chip (MPSoC) and shortening time-to- market projections, Transaction Level Modeling and Platform Aware Design are seen as...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
In this paper, a novel design space exploration approach is proposed that enables a concurrent optimization of the topology, the process binding, and the communication routing of ...
FPT
2005
IEEE
13 years 10 months ago
2005
IEEE
We describe a communication-centric design methodology with SystemC that allows for efficient FPGA prototype generation of transaction level models (TLM). Using a framework compr...