190 search results - page 2 / 38 » Automatically Mapping Code on an Intelligent Memory Architec... |
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
DAC
2007
ACM
14 years 5 months ago
2007
ACM
Programming multi-processor systems-on-chip (MPSoC) involves partitioning and mapping of sequential reference code onto multiple parallel processing elements. The immense potentia...
CDES
2006
13 years 6 months ago
2006
- Many memory-sensitive embedded applications can tolerate small performance degradations if doing so can reduce the memory space requirements significantly. This paper explores th...
SAMOS
2005
Springer
13 years 10 months ago
2005
Springer
This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. P...
SAC
2002
ACM
13 years 4 months ago
2002
ACM
This paper presents a novel approach for the problem of generating tiled code for nested for-loops using a tiling transformation. Tiling or supernode transformation has been widel...