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FPL
2004
Springer
101views Hardware» more  FPL 2004»
13 years 11 months ago
Automatic Creation of Reconfigurable PALs/PLAs for SoC
Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run -time reconfigurabil...
Mark Holland, Scott Hauck
ICCAD
2004
IEEE
114views Hardware» more  ICCAD 2004»
14 years 2 months ago
High-level synthesis using computation-unit integrated memories
Abstract— High-level synthesis (HLS) of memory-intensive applications has featured several innovations in terms of enhancements made to the basic memory organization and data lay...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...
FPL
2009
Springer
115views Hardware» more  FPL 2009»
13 years 10 months ago
Recursion in reconfigurable computing: A survey of implementation approaches
Reconfigurable systems are widely used nowadays to increase performance of computationally intensive applications. There exist a lot of synthesis tools that automatically generate...
Iouliia Skliarova, Valery Sklyarov
DAC
2002
ACM
14 years 6 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...
DAC
2000
ACM
13 years 10 months ago
Block placement with symmetry constraints based on the O-tree non-slicing representation
The ordered tree (O-tree) representation has recently gained much interest in layout design automation. Different from previous topological representations of non-slicing floorpl...
Yingxin Pang, Florin Balasa, Koen Lampaert, Chung-...