20 search results - page 1 / 4 » BIST Based Interconnect Fault Location for FPGAs |
FPL
2004
Springer
13 years 10 months ago
2004
Springer
This paper presents a novel approach to interconnect fault location for FPGAs during power-on sequence. The method is based on a concept known as fault grading which utilizes defec...
CSREAESA
2009
13 years 5 months ago
2009
Two embedded processor based fault injection case studies are presented which are applicable to Field Programmable Gate Arrays (FPGAs) and FPGA cores in configurable System-on-Chip...
ITC
1998
IEEE
13 years 9 months ago
1998
IEEE
: We introduce the first BIST approach for testing the programmable routing network in FPGAs. Our method detects opens in, and shorts among, wiring segments, and also faults affect...
DFT
2009
IEEE
13 years 11 months ago
2009
IEEE
This paper presents the first implementation of Built-In Self-Test (BIST) of Field Programmable Gate Arrays (FPGAs) using a soft core embedded processor for reconfiguration of the...
VTS
2006
IEEE
13 years 10 months ago
2006
IEEE
We tackle the problem of fault-free assumptions in current PLB and interconnect built-in-self-test (BIST) techniques for FPGAs. These assumptions were made in order to develop stro...