55 search results - page 1 / 11 » Balancing Logic Utilization and Area Efficiency in FPGAs |
FPL
2000
Springer
13 years 8 months ago
2000
Springer
Abstract. In this paper we outline a procedure to determine appropriate partitioning of programmable logic and interconnect area to minimize overall device area across a broad rang...
TVLSI
2010
12 years 11 months ago
2010
There is a dramatic logic density gap between FPGAs and ASICs, and this gap is the main reason FPGAs are not cost-effective in high volume applications. Modern FPGAs narrow this ga...
FPGA
2004
ACM
13 years 8 months ago
2004
ACM
Pattern matching for network security and intrusion detection demands exceptionally high performance. Much work has been done in this field, and yet there is still significant roo...
FPL
2005
Springer
13 years 10 months ago
2005
Springer
As the logic capacity of FPGA increases, there has been a corresponding increase in the variety of FPGA building blocks. From a mere collection of the conventional logic blocks, F...
ICCAD
2007
IEEE
14 years 1 months ago
2007
IEEE
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...