Sciweavers

47 search results - page 2 / 10
» Bandwidth-Constrained Mapping of Cores onto NoC Architecture...
Sort
View
ICCD
2007
IEEE
105views Hardware» more  ICCD 2007»
13 years 8 months ago
Power-aware mapping for reconfigurable NoC architectures
A core mapping method for reconfigurable network-on-chip (NoC) architectures is presented in this paper. In most of the existing methods, mapping is carried out based on the traff...
Mehdi Modarressi, Hamid Sarbazi-Azad
PPL
2008
185views more  PPL 2008»
13 years 4 months ago
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...
ISCAS
2005
IEEE
127views Hardware» more  ISCAS 2005»
13 years 10 months ago
Energy and latency evaluation of NoC topologies
Abstract — Mapping applications onto different networks-onchip (NoCs) topologies is done by mapping processing cores on local ports of routers considering requirements like laten...
Márcio Eduardo Kreutz, César A. M. M...
VLSI
2005
Springer
13 years 10 months ago
Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs
This work addresses the problem of application mapping in networks-on-chip (NoCs) having as goal to minimize the total dynamic energy consumption of a complex system-on-a-chip (So...
César A. M. Marcon, José Carlos S. P...
CODES
2006
IEEE
13 years 11 months ago
Layout aware design of mesh based NoC architectures
Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology suc...
Krishnan Srinivasan, Karam S. Chatha