54 search results - page 9 / 11 » Biologically-Inspired Optimization of Circuit Performance an... |
ICCAD
2007
IEEE
14 years 2 months ago
2007
IEEE
Late CMOS scaling reduces device reliability, and existing work has studied the permanent SER (soft error rate) for configuration memory in FPGA extensively. In this paper, we sh...
HPCA
2009
IEEE
14 years 2 days ago
2009
IEEE
As transistor process technology approaches the nanometer scale, process variation significantly affects the design and optimization of high performance microprocessors. Prior stu...
DAC
2005
ACM
14 years 6 months ago
2005
ACM
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
DAC
2005
ACM
14 years 6 months ago
2005
ACM
The race conditions often limit the smallest feasible clock period that the optimal clock skew scheduling can achieve. Therefore, the combination of clock skew scheduling and dela...
TON
2010
13 years 3 months ago
2010
—p-Cycles have been proposed for preprovisioned 1 : N protection in optical mesh networks. Although the protection circuits are preconfigured, the detection of failures and the ...