68 search results - page 12 / 14 » Buffered Crossbar Fabrics Based on Networks on Chip |
ISLPED
2000
ACM
13 years 10 months ago
2000
ACM
In this paper we present a completely on-chip voltage regulation technique which promises to adjust the degree of voltage regulation in a digital logic chip in the face of process...
DAC
2009
ACM
13 years 10 months ago
2009
ACM
Process scaling has given designers billions of transistors to work with. As feature sizes near the atomic scale, extensive variation and wearout inevitably make margining unecono...
ISCAS
2005
IEEE
13 years 11 months ago
2005
IEEE
Abstract- This paper describes the implementation of an areaefficient and protected user memory-mapped network interface, the pbuf (Parcel Buffer), for the Data IntensiVe Architect...
SIGCOMM
2003
ACM
13 years 11 months ago
2003
ACM
Routers built around a single-stage crossbar and a centralized scheduler do not scale, and (in practice) do not provide the throughput guarantees that network operators need to ma...
FPL
2005
Springer
13 years 11 months ago
2005
Springer
This paper addresses exploitation of the capabilities of platform FPGAs to implement embedded networking for systems on chip. In particular, a methodology for exploring trade-offs...