63 search results - page 2 / 13 » CMOS gate modeling based on equivalent inverter |
ISCAS
2002
IEEE
13 years 9 months ago
2002
IEEE
- In this paper, new formulations for the energy dissipation of lossy transmission lines driven by CMOS inverters are provided. These formulations are obtained using an approximate...
GLVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
—Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effectiv...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
Predictive delay analysis is presented for a representative CMOS inverter with submicron device size using PREDICTMOS MOSFET model. As against SPICE, which adopts a time consuming...
ISCAS
2006
IEEE
13 years 10 months ago
2006
IEEE
A novel 0. 13,um CMOS integrated linear voltage to pulse delay time converter (VTC) is proposed. The VTC ml architecture uses current starved inverters where the inverter delay ver...
GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
A new circuit technique based on a single PMOS sleep transistor and a dual threshold voltage CMOS technology is proposed in this paper for simultaneously reducing subthreshold and...