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GLVLSI
2003
IEEE

Shielding effect of on-chip interconnect inductance

9 years 5 months ago
Shielding effect of on-chip interconnect inductance
—Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effective capacitance of an load driven by a CMOS inverter is presented. The interconnect inductance decreases the gate delay and increases the time required for the signal to propagate across an interconnect, reducing the overall delay to drive an load. Ignoring the line inductance overestimates the circuit delay, inefficiently oversizing the circuit driver. Considering line inductance in the design process saves gate area, reducing dynamic power dissipation. Average reductions in power of 17% and area of 29% are achieved for example circuits. An accurate model for a CMOS inverter and an load is used to characterize the propagation delay. The accuracy of the delay model is within an average error of less than 9% as compared to SPICE.
Magdy A. El-Moursy, Eby G. Friedman
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where GLVLSI
Authors Magdy A. El-Moursy, Eby G. Friedman
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