Sciweavers

Share
13 search results - page 1 / 3
» CMP-aware Maze Routing Algorithm for Yield Enhancement
Sort
View
ASPDAC
2005
ACM
114views Hardware» more  ASPDAC 2005»
10 years 6 months ago
Redundant-via enhanced maze routing for yield improvement
- Redundant via insertion is a good solution to reduce the yield loss by via failure. However, the existing methods are all post-layout optimizations that insert redundant via afte...
Gang Xu, Li-Da Huang, David Z. Pan, Martin D. F. W...
ISVLSI
2007
IEEE
161views VLSI» more  ISVLSI 2007»
10 years 10 months ago
CMP-aware Maze Routing Algorithm for Yield Enhancement
— Chemical-Mechanical Polishing (CMP) is one of the key steps during nanometer VLSI manufacturing process where minimum variation of layout pattern densities is desired. This pap...
Hailong Yao, Yici Cai, Xianlong Hong
ISPD
1999
ACM
106views Hardware» more  ISPD 1999»
10 years 8 months ago
Timing driven maze routing
—This paper studies a natural formulation of the timing-driven maze routing problem. A multigraph model appropriate for global routing applications is adopted; the model naturall...
Sung-Woo Hur, Ashok Jagannathan, John Lillis
TCAD
2008
119views more  TCAD 2008»
10 years 4 months ago
Full-Chip Routing Considering Double-Via Insertion
As the technology node advances into the nanometer era, via-open defects are one of the dominant failures due to the copper cladding process. To improve via yield and reliability, ...
Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lum...
DAC
2004
ACM
10 years 9 months ago
Optical proximity correction (OPC): friendly maze routing
As the technology migrates into the deep submicron manufacturing (DSM) era, the critical dimension of the circuits is getting smaller than the lithographic wavelength. The unavoid...
Li-Da Huang, Martin D. F. Wong
books