6 search results - page 1 / 2 » Cascaded time difference amplifier using differential logic ... |
ASPDAC
2010
ACM
13 years 3 months ago
2010
ACM
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
— A phase-locked loop (PLL) with two different delay feedback paths is presented. It provides a new approach to minimize the dead zone, jitter accumulation, long settling time an...
CHES
2006
Springer
13 years 9 months ago
2006
Springer
In recent years, some countermeasures against Differential Power Analysis (DPA) at the logic level have been proposed. At CHES 2005 conference, Popp and Mangard proposed a new coun...
ICCAD
1995
IEEE
13 years 8 months ago
1995
IEEE
ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Power gating is one of the most effective techniques in reducing the standby leakage current of VLSI circuits. In this paper we introduce a new approach for sleep transistor sizin...