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» Charge sharing fault analysis and testing for CMOS domino lo...
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ATS
2000
IEEE
149views Hardware» more  ATS 2000»
13 years 9 months ago
Charge sharing fault analysis and testing for CMOS domino logic circuits
Because domino logic design offers smaller area and faster delay than conventional CMOS design, it is very popular in the high-performance processor design. However, domino logic ...
Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Sh...
DFT
2000
IEEE
105views VLSI» more  DFT 2000»
13 years 9 months ago
Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits
Because domino logic design offers smaller area and higher speed than complementary CMOS design, it has been very popularly used to design highperformance processors. However: dom...
Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang...
ICCAD
2000
IEEE
72views Hardware» more  ICCAD 2000»
13 years 9 months ago
Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation
The Charge Sharing (CS) problem is one of notorious noise problems in domino circuits design and test. In this paper, this problem is thoroughly investigated by considering circui...
Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen...
ICCAD
2003
IEEE
135views Hardware» more  ICCAD 2003»
13 years 10 months ago
ATPG for Noise-Induced Switch Failures in Domino Logic
Domino circuits have been used in most modern high-performance microprocessor designs because of their high speed, low transistor-count and hazard-free operation. However, with te...
Rahul Kundu, R. D. (Shawn) Blanton
ITC
2003
IEEE
167views Hardware» more  ITC 2003»
13 years 10 months ago
Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk
A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of...
Rahul Kundu, R. D. (Shawn) Blanton