41 search results - page 1 / 9 » Circuit styles and strategies for CMOS VLSI design on SOI |
ISLPED
1999
ACM
13 years 9 months ago
1999
ACM
GLVLSI
2005
IEEE
13 years 10 months ago
2005
IEEE
We present simulations for ultra-thin body, fully-depleted, double-gate (DG) silicon-on-insulator (SOI) devices that can be readily optimized for both static power loss and perfor...
ISVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
SOI (silicon-on-insulator) technology suffers from a number of floating body effects, most notably parasitic bipolar and history effects. These are influenced by the rapidly incre...
ISVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
A new hybrid CMOS-nanoscale circuit style has been developed that uses only one type of Field Effect Transistor (FET) in the logic portions of a design. This is enabled by CMOS pro...
ISLPED
2003
ACM
13 years 10 months ago
2003
ACM
Static and dynamic power for strained-Si device is analyzed and compared with conventional bulk-Si technology. Optimum device design points are suggested with controlling physical...