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» Classbased Detailed Routing in VLSI Design
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COLOGNETWENTE
2008
13 years 6 months ago
Classbased Detailed Routing in VLSI Design
Christian Schulte 0002, Tim Nieberg
DAC
2011
ACM
12 years 5 months ago
AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection
In the era of deep sub-wavelength lithography for nanometer VLSI designs, manufacturability and yield issues are critical and need to be addressed during the key physical design i...
Duo Ding, Jhih-Rong Gao, Kun Yuan, David Z. Pan
DAC
2008
ACM
14 years 6 months ago
ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction
In this paper, we present ELIAD, an efficient lithography aware detailed router to optimize silicon image after optical proximity correction (OPC) in a correct-by-construction man...
Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan
GLVLSI
2009
IEEE
131views VLSI» more  GLVLSI 2009»
14 years 3 days ago
Octilinear redistributive routing in bump arrays
This paper proposes a scheme for automatic re-distribution layer (RDL) routing, which is used in chip-package connections. Traditional RDL routing designs are mostly performed man...
Renshen Wang, Chung-Kuan Cheng
DAC
2007
ACM
14 years 6 months ago
An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design
The flip-chip package provides a high chip-density solution to the demand for more I/O pads of VLSI designs. In this paper, we present the first routing algorithm in the literatur...
Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang