14 search results - page 2 / 3 » Classbased Detailed Routing in VLSI Design |
GLVLSI
2000
IEEE
13 years 9 months ago
2000
IEEE
We present a novel global routing and cross-point assignment methodology for sea-of-gates (SOG) designs. Using the proposed congestion driven spanning trees (CDST), and continuous...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
same level of system-level CAD support that is now commonplace in the IC industry.Recent advances in microfluidics are expected to lead to sensor systems for high-throughput bioche...
DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectiv...
ISPD
2005
ACM
13 years 11 months ago
2005
ACM
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
FPGA
2004
ACM
13 years 10 months ago
2004
ACM
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and sh...