191 search results - page 1 / 39 » Clock Distribution Design in VLSI Circuits. An Overview |
ISCAS
1993
IEEE
13 years 9 months ago
1993
IEEE
GLVLSI
1998
IEEE
13 years 9 months ago
1998
IEEE
GLVLSI
2006
IEEE
13 years 11 months ago
2006
IEEE
A sensitivity analysis of resonant H-tree clock distribution networks is presented in this paper for a TSMC 0.18 μm CMOS technology. The analysis focuses on the effect of the dri...
DFT
2006
IEEE
13 years 11 months ago
2006
IEEE
In this paper we will introduce a novel approach for the on-chip generation of a faulttolerant clock. We will motivate why it becomes more and more desirable to provide VLSI circu...
GLVLSI
2010
IEEE
13 years 9 months ago
2010
IEEE
This paper presents a self-compensation scheme of manufacturing variability for clock skew reduction. In the proposed scheme, a CDN with embedded variability sensors tunes variabl...