15 search results - page 3 / 3 » Clock Synchronization in Cell BE Traces |
GLVLSI
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as c...
ASYNC
2000
IEEE
13 years 9 months ago
2000
IEEE
Self-timed systems often have to communicate with their environment through a clocked interface. For example, off-chip memory may require clocking and this can reduce the benefit...
ISCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
Abstract—We present a silicon neuron that uses shunting inhibition (conductance-based) with a synaptic rise-time to achieve synchrony. Synaptic rise-time promotes synchrony by de...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
- Power consumption is one of the major challenges in VLSI Design. Power constrained designs need tools to accurately predict the power consumption and provide feedback to designer...
Publication
Global Positioning System (GPS) Technology allows precise determination of location, velocity, direction, and time. The price of GPS receivers is falling rapidly and the applicatio...