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» Clock buffer and wire sizing using sequential programming
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DAC
2006
ACM
10 years 5 months ago
Clock buffer and wire sizing using sequential programming
This paper investigates methods for clock skew minimization using buffer and wire sizing. First, a technique that significantly improves solution quality and stability of sequent...
Matthew R. Guthaus, Dennis Sylvester, Richard B. B...
DAC
2010
ACM
9 years 10 months ago
Non-uniform clock mesh optimization with linear programming buffer insertion
Clock meshes are extremely effective at filtering clock skew from environmental and process variations. For this reason, clock meshes are used in most high performance designs. Ho...
Matthew R. Guthaus, Gustavo Wilke, Ricardo Reis
ISQED
2002
IEEE
111views Hardware» more  ISQED 2002»
10 years 4 months ago
Optimization of the Power/Ground Network Wire-Sizing and Spacing Based on Sequential Network Simplex Algorithm
This paper presents a fast algorithm to optimize both the widths and lengths of power/ground networks under reliability and power dip/ground bounce constraints. The spacesizing wh...
Ting-Yuan Wang, Charlie Chung-Ping Chen
ASPDAC
2008
ACM
129views Hardware» more  ASPDAC 2008»
10 years 1 months ago
Clock tree synthesis with data-path sensitivity matching
This paper investigates methods for minimizing the impact of process variation on clock skew using buffer and wire sizing. While most papers on clock trees ignore data-path circuit...
Matthew R. Guthaus, Dennis Sylvester, Richard B. B...
ISCAS
2005
IEEE
138views Hardware» more  ISCAS 2005»
10 years 5 months ago
Transition time bounded low-power clock tree construction
— Recently power becomes a significant issue in clock network design for high-performance ICs because the clock network consumes a large portion of the total power in the whole s...
Min Pan, Chris C. N. Chu, J. Morris Chang
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