13 search results - page 1 / 3 » Clock buffer and wire sizing using sequential programming |
DAC
2006
ACM
13 years 10 months ago
2006
ACM
This paper investigates methods for clock skew minimization using buffer and wire sizing. First, a technique that significantly improves solution quality and stability of sequent...
DAC
2010
ACM
13 years 2 months ago
2010
ACM
Clock meshes are extremely effective at filtering clock skew from environmental and process variations. For this reason, clock meshes are used in most high performance designs. Ho...
ISQED
2002
IEEE
13 years 9 months ago
2002
IEEE
This paper presents a fast algorithm to optimize both the widths and lengths of power/ground networks under reliability and power dip/ground bounce constraints. The spacesizing wh...
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
This paper investigates methods for minimizing the impact of process variation on clock skew using buffer and wire sizing. While most papers on clock trees ignore data-path circuit...
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
— Recently power becomes a significant issue in clock network design for high-performance ICs because the clock network consumes a large portion of the total power in the whole s...