6 search results - page 1 / 2 » Clock-frequency assignment for multiple clock domain systems... |
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Modern systems-on-a-chip platforms support multiple clock domains, in which different sub-circuits are driven by different clock signals. Although the frequency of each domain can...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
—Partial Reconfiguration (PR) of FPGAs presents many opportunities for application design flexibility, enabling tasks to dynamically swap in and out of the FPGA without entire sy...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
The application of general clock skew scheduling is practically limited due to the difficulties in implementing a wide spectrum of dedicated clock delays in a reliable manner. Th...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
IPPS
1998
IEEE
13 years 9 months ago
1998
IEEE
With aggressive superscalar processors delivering diminishing returns, alternate designs that make good use of the increasing chip densities are actively being explored. One such ...