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ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
10 years 10 months ago
Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design
– Many embedded system designs usually impose (hard) read-time constraints on tasks. Thus, computing a tight upper bound of the worst case execution time (WCET) of a software is ...
Junhyung Um, Taewhan Kim
CASES
2010
ACM
9 years 11 months ago
Improved procedure placement for set associative caches
The performance of most embedded systems is critically dependent on the memory hierarchy performance. In particular, higher cache hit rate can provide significant performance boos...
Yun Liang, Tulika Mitra
CASES
2010
ACM
9 years 11 months ago
Balancing memory and performance through selective flushing of software code caches
Dynamic binary translators (DBTs) are becoming increasingly important because of their power and flexibility. However, the high memory demands of DBTs present an obstacle for all ...
Apala Guha, Kim M. Hazelwood, Mary Lou Soffa
LCTRTS
2007
Springer
10 years 7 months ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...
CODES
2008
IEEE
10 years 3 months ago
Application specific non-volatile primary memory for embedded systems
Memory subsystems have been considered as one of the most critical components in embedded systems and furthermore, displaying increasing complexity as application requirements div...
Kwangyoon Lee, Alex Orailoglu
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