14 search results - page 3 / 3 » Combining Retiming and Recycling to Optimize the Performance... |
ICCAD
1998
IEEE
13 years 9 months ago
1998
IEEE
Abstract Althoughtremendousadvanceshave been accomplished in logic synthesis in the past two decades, in some cases logic synthesis still cannot attain the improvements possible by...
ENTCS
2008
13 years 4 months ago
2008
This paper reports on the design of a test chip built to test a) a new latency insensitive network fabric protocol and circuits, b) a new synchronizer design, and c) how efficient...
NOCS
2008
IEEE
13 years 11 months ago
2008
IEEE
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
ICCD
1997
IEEE
13 years 8 months ago
1997
IEEE
Asynchronous systems are being viewed as an increasingly viable alternative to purely synchronous systems. This paper gives an overview of the current state of the art in practica...