22 search results - page 1 / 5 » Compact structural test generation for analog macros |
DATE
1997
IEEE
13 years 8 months ago
1997
IEEE
A structural, fault-model based methodology for the generation of compact high-quality test sets for analog macros is presented. Results are shown for an IVconverter macro design....
ATS
1996
IEEE
13 years 8 months ago
1996
IEEE
A hierarchical test generation method is presented that uses the inherent hierarchical structure of the circuit under test and takes fault diagnosability into account right from t...
ASPDAC
2006
ACM
13 years 10 months ago
2006
ACM
This paper advances a new methodology based on signal-path information to resolve the problem of device-level placement for analog layout. This methodology is mainly based on three...
CIKM
2008
Springer
13 years 6 months ago
2008
Springer
In the past, quite a few fast algorithms have been developed to mine frequent patterns over graph data, with the large spectrum covering many variants of the problem. However, the...
ATS
2009
IEEE
13 years 11 months ago
2009
IEEE
SAT-based automatic test pattern generation has several advantages compared to conventional structural procedures, yet often yields too large test sets. We present a dynamic compa...