Sciweavers

559 search results - page 2 / 112
» Compiling Image Processing Applications to Reconfigurable Ha...
Sort
View
CODES
1996
IEEE
13 years 9 months ago
Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine
The partitioning of image processing algorithms with a novel hardware/software co-designframework (CoDe-X) is presented in this paper, where a new Xputer-architecture (parallel Ma...
Reiner W. Hartenstein, Jürgen Becker, Rainer ...
CASES
2006
ACM
13 years 9 months ago
Incremental elaboration for run-time reconfigurable hardware designs
We present a new technique for compiling run-time reconfigurable hardware designs. Run-time reconfigurable embedded systems can deliver promising benefits over implementations in ...
Arran Derbyshire, Tobias Becker, Wayne Luk
FCCM
2004
IEEE
102views VLSI» more  FCCM 2004»
13 years 9 months ago
Smart Camera Based on Reconfigurable Hardware Enables Diverse Real-Time Applications
We demonstrate the use of a "smart camera" to accelerate two very different image processing applications. The smart camera consists of a high quality video camera and f...
Miriam Leeser, Shawn Miller, Haiqian Yu
MJ
2006
145views more  MJ 2006»
13 years 5 months ago
A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems
In this paper, we propose a method for speeding-up Digital Signal Processing applications by partitioning them between the reconfigurable hardware blocks of different granularity ...
Michalis D. Galanis, Athanasios Milidonis, Athanas...
AICCSA
2007
IEEE
89views Hardware» more  AICCSA 2007»
13 years 11 months ago
Software/Configware Implementation of Combinatorial Algorithms
This paper discusses an approach for solving combinatorial problems by combining software and dynamically reconfigurable hardware (configware). The suggested technique avoids inst...
Iouliia Skliarova, Valery Sklyarov