Sciweavers

14 search results - page 2 / 3
» Concurrent Error Detection in Self-Timed VLSI
Sort
View
CHES
2004
Springer
170views Cryptology» more  CHES 2004»
13 years 10 months ago
Concurrent Error Detection Schemes for Involution Ciphers
Because of the rapidly shrinking dimensions in VLSI, transient and permanent faults arise and will continue to occur in the near future in increasing numbers. Since cryptographic c...
Nikhil Joshi, Kaijie Wu, Ramesh Karri
DFT
2002
IEEE
103views VLSI» more  DFT 2002»
13 years 10 months ago
Input Ordering in Concurrent Checkers to Reduce Power Consumption
A novel approach for reducing power consumption in checkers used for concurrent error detection is presented. Spatial correlations between the outputs of the circuit that drives t...
Kartik Mohanram, Nur A. Touba
DFT
2008
IEEE
103views VLSI» more  DFT 2008»
13 years 11 months ago
Arbitrary Error Detection in Combinational Circuits by Using Partitioning
The paper presents a new technique for designing a concurrently checking combinational circuit. The technique is based on partitioning the circuit into two independent sub-circuit...
Osnat Keren, Ilya Levin, Vladimir Ostrovsky, Beni ...
VLSID
2003
IEEE
82views VLSI» more  VLSID 2003»
14 years 5 months ago
SPaRe: Selective Partial Replication for Concurrent Fault Detection in FSMs
We propose a non-intrusive methodology for concurrent fault detection in FSMs. The proposed method is similar to duplication, wherein a replica of the circuit acts as a predictor ...
Petros Drineas, Yiorgos Makris
DFT
2003
IEEE
117views VLSI» more  DFT 2003»
13 years 10 months ago
Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code
We describe a method for designing fault tolerant circuits based on an extension of a Concurrent Error Detection (CED) technique. The proposed extension combines parity check code...
Sobeeh Almukhaizim, Yiorgos Makris