Sciweavers

62 search results - page 1 / 13
» Concurrent Fault Detection in Random Combinational Logic
Sort
View
ISQED
2003
IEEE
134views Hardware» more  ISQED 2003»
13 years 10 months ago
Concurrent Fault Detection in Random Combinational Logic
We discuss a non-intrusive methodology for concurrent fault detection in random combinational logic. The proposed method is similar to duplication, wherein a replica of the circui...
Petros Drineas, Yiorgos Makris
DATE
2008
IEEE
75views Hardware» more  DATE 2008»
13 years 11 months ago
A low-cost concurrent error detection technique for processor control logic
This paper presents a concurrent error detection technique targeted towards control logic in a processor with emphasis on low area overhead. Rather than detect all modeled transie...
Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srin...
DFT
2003
IEEE
117views VLSI» more  DFT 2003»
13 years 10 months ago
Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code
We describe a method for designing fault tolerant circuits based on an extension of a Concurrent Error Detection (CED) technique. The proposed extension combines parity check code...
Sobeeh Almukhaizim, Yiorgos Makris
DDECS
2007
IEEE
121views Hardware» more  DDECS 2007»
13 years 11 months ago
A Novel Parity Bit Scheme for SBox in AES Circuits
– This paper addresses an efficient concurrent fault detection scheme for the SBox hardware implementation of the AES algorithm. Concurrent fault detection is important not only ...
Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouze...
ICCAD
1990
IEEE
105views Hardware» more  ICCAD 1990»
13 years 9 months ago
Partial Detectability Profiles
Partial detectability profiles are formed by randomly sampling each fault's detectability and are used in estimating the fault coverage of random input test vectors on combin...
Paul G. Ryan, W. Kent Fuchs