10 search results - page 1 / 2 » Concurrent logic restructuring and placement for timing clos... |
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
: In this paper, an algorithm for simultaneous logic restructuring and placement is presented. This algorithm first constructs a set of super-cells along the critical paths and the...
ICCAD
2001
IEEE
14 years 1 months ago
2001
IEEE
Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation...
GLVLSI
2008
IEEE
13 years 11 months ago
2008
IEEE
Timing optimizations during logic synthesis has become a necessary step to achieve timing closure in VLSI designs. This often involves “shortening” all paths found in the circ...
TCAD
2008
13 years 4 months ago
2008
The relatively poor scaling of interconnect in modern digital circuits necessitates a number of design optimizations, which must typically be iterated several times to meet the spe...
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
—In this paper, we present a new block budgeting algorithm which speeds up timing closure in timing driven hierarchical flows. After a brief description of the addressed flow, ...