18 search results - page 2 / 4 » Congestion Estimation with Buffer Planning in Floorplan Desi... |
ASPDAC
2007
ACM
13 years 10 months ago
2007
ACM
- Advanced process technologies impose more significant challenges especially when manufactured circuits exhibit substantial process variations. Consideration of process variations...
DAC
2008
ACM
14 years 7 months ago
2008
ACM
Due to skewed scaling of interconnect delay and cell delay with technology scaling, modern VLSI timing closure requires use of extensive buffer insertion. Inserting a large number...
ISQED
2002
IEEE
13 years 11 months ago
2002
IEEE
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...
ASPDAC
2004
ACM
13 years 11 months ago
2004
ACM
Congestion estimation is an important issue for the success of the VLSI layout. Fast congestion estimation provides an efficient means to adjust the placement and wire planning. A...
GLVLSI
2000
IEEE
13 years 10 months ago
2000
IEEE
In many applications such as high-level synthesis (HLS) and logic synthesis and possibly engineering change order (ECO) we would like to get fast and accurate estimations of diffe...