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» Constraint Analysis for DSP Code Generation
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ISSS
1999
IEEE
85views Hardware» more  ISSS 1999»
13 years 10 months ago
Efficient Scheduling of DSP Code on Processors with Distributed Register Files
Code generation methods for digital signal processors are increasingly hampered by the combination of tight timing constraints imposed by the algorithms and the limited capacity o...
Bart Mesman, Carlos A. Alba Pinto, Koen Van Eijk
VLSID
1999
IEEE
99views VLSI» more  VLSID 1999»
13 years 10 months ago
Array Index Allocation under Register Constraints in DSP Programs
Abstract Code optimization for digital signal processors DSPs has been identi ed as an important new topic in system-level design of embedded systems. Both DSP processors and algor...
Anupam Basu, Rainer Leupers, Peter Marwedel
ICPP
2002
IEEE
13 years 10 months ago
Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications
Code size expansion of software-pipelined loops is a critical problem for DSP systems with strict code size constraint. Some ad-hoc code size reduction techniques were used to try...
Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha
DAC
1997
ACM
13 years 10 months ago
Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures
—Many application-specific architectures provide indirect addressing modes with auto-increment/decrement arithmetic. Since these architectures generally do not feature an indexe...
Ashok Sudarsanam, Stan Y. Liao, Srinivas Devadas
CODES
2003
IEEE
13 years 11 months ago
Design space minimization with timing and code size optimization for embedded DSP
One of the most challenging problems in high-level synthesis is how to quickly explore a wide range of design options to achieve high-quality designs. This paper presents an Integ...
Qingfeng Zhuge, Zili Shao, Bin Xiao, Edwin Hsing-M...